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[June 20, 2013]
VeriSilicon Announces ZSP G4 Architecture and ZSP981 Core
SHANGHAI, Jun 20, 2013 (PR Newswire Europe via COMTEX) -- -- An Innovative DSP with Optimal Performance, Power and Area for Advanced Wireless Technologies SHANGHAI, June 20, 2013 /PRNewswire/ -- VeriSilicon Holdings Co., Ltd. (VeriSilicon), a leading Custom Silicon Solutions and Semiconductor IP provider, today announced the introduction of its fourth generation ZSP architecture (ZSP G4) and the availability of the ZSP981 Digital Signal Processor (DSP), the first core in the ZSP G4 series. The ZSP G4 architecture is compatible with the previous generation architecture and extends it further by introducing vector computation capabilities, higher bandwidth interfaces and more execution resources. Designed with inputs from wireless industry experts, the ZSP981 offers a 17X performance improvement over third generation ZSP cores while providing the power efficiency needed for mobile devices. ZSP981 provides modem developers the right level of programmable signal processing capability to implement new and evolving wireless technologies such as LTE-Advanced (LTE-A), 802.11ac and more.
ZSP981 is the first of a set of cores based on the ZSP G4 architecture family. The cores range from a 4-issue, 4-MAC scalar core to a 6-issue, 260-MAC vector core. The cores differ primarily in their performance, power and area characteristics. They offer the flexibility and scalability necessary to target evolving application needs. Developers can easily select a DSP core from the ZSP G4 family that best satisfies the power, performance, area and flexibility considerations of the target platform. In addition, they can define custom instructions to exercise user defined hardware via the enhanced Z.Turbo interface. Cores based on ZSP G4 are ideally suited for multi-mode terminals, femto-cells, smart grid, M2M and mobile infrastructure.
ZSP981 is a fully synthesizable, 6-issue superscalar DSP core. Running at 1.2 GHz, a single ZSP981 can deliver 82 billion multiply accumulate operations per second. With wide, high speed interfaces to shared memory and enhanced Z.Turbo coprocessor ports to hardware accelerators, the ZSP981 enables system designers to achieve the desired balance between software and hardware in their systems. Also included in the ZSP981 subsystem are a power management module, a multi-core communication module and a multichannel Direct Memory Access (DMA), which greatly simplify system level integration and development.
"A pure Software Defined Radio (SDR) approach presents power challenges in mobile devices. User equipment system developers seek an optimal balance between performance and power, which is made possible by our ZSP981 DSP core," says Dr. Wayne Dai, President and CEO of VeriSilicon. "Based on the ZSP G4 architecture, we have created an adaptive and scalable wireless platform that can help mobile communication SoC vendors achieve the best solution in the shortest time." The ZSP981 architecture is supported by ZView(TM), a full-featured, easy-to-use suite of tools consisting of an Integrated Development Environment (IDE), compiler, assembler, optimizer, linker, debugger, simulators, and profiling utilities. ZView(TM) incorporates a number of significant new enhancements, including a vectorizing C compiler, and other optimization tools to accelerate software development.
A set of wireless signal processing libraries optimized on ZSP981 are also available to help users reduce their time to market. VeriSilicon will demonstrate real time streaming High Definition (HD) video playback via LTE-A physical layer running on ZSP981 at GSMA Mobile Asia Expo in Shanghai in June 2013.
For more information, please visit www.verisilicon.com/ZSP981.html [
] or contact email@example.com [mailto:firstname.lastname@example.org] CONTACT: VeriSilicon Marketing, Miya Kong, +86-135-9026-2584,email@example.com Web site:
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