[April 06, 2012]

U.S. Patents Awarded to Inventors in Oregon (April 6)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., April 6 -- The following federal patents were awarded to inventors in Oregon.

*** Xerox Assigned Patent for Color Printing ALEXANDRIA, Va., April 6 -- Xerox, Norwalk, Conn., has been assigned a patent (8,149,454) developed by four co-inventors for a color printing. The co-inventors are Meng Yao, West Linn, Ore., Michael T. Stevens, Aloha, Ore., Paul W. Philippi, Sherwood, Ore., and Michael D. Stevens, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of operating a color printer including using a first set of one-dimensional TRCs or a second set of one-dimensional TRCs with a single set of color tables." The patent application was filed on June 9, 2005 (11/149,599). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,454&OS=8,149,454&RS=8,149,454 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Digimarc Assigned Patent ALEXANDRIA, Va., April 6 -- Digimarc, Beaverton, Ore., has been assigned a patent (8,149,458) developed by Alastair M. Reed, Lake Oswego, Ore., for "methods and apparatuses for printer calibration." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A test pattern printed by a printer is assessed--without colorimetric equipment--to provide data used in recalibrating the printer. The assessment may be made by an unskilled operator, and can include discerning whether a particular pattern is visible in the printed test pattern, or whether a feature in the test pattern is relatively wider or narrower. From such assessment, needed changes to the printer's calibration data are inferred and implemented. A variety of other printer calibration techniques are disclosed. The technology is illustrated in the context of dye sublimation printers, and is particularly useful in optimizing printing of digitally-watermarked graphics." The patent application was filed on Oct. 28, 2008 (12/259,720). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,458&OS=8,149,458&RS=8,149,458 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Sharp Laboratories of America Assigned Patent ALEXANDRIA, Va., April 6 -- Sharp Laboratories of America, Camas, Wash., has been assigned a patent (8,149,448) developed by Tommy L. Oswald, Tigard, Ore., for "systems and methods for rapidly creating an image from a document." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of rapidly creating an image from a document is disclosed. Image data derived from a document is received at an imaging device. It is then determined whether the image data is in an image-ready format that can be directly processed by a marking engine. If the image data is in an image-ready format, it is transmitted to the marking engine to create an image. If it is not in an image-ready format, the image data is converted to a proper format. The image data is transmitted to the marking engine. If the image data is spooled to a nonvolatile storage device, the spooling takes place only after or concurrent with transmission of the image data to the marking engine such that creation of the image is not delayed by this spooling process." The patent application was filed on Aug. 31, 2005 (11/216,893). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,448&OS=8,149,448&RS=8,149,448 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Intel Assigned Patent for Millimeter-wave Communication System with Directional Antenna and One or More Millimeter-wave Reflectors ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,149,178) developed by Siavash M. Alamouti, Hillsboro, Ore., Alexander Alexandrovich Maltsev, Nizhny Novgorod, Russia, and Vadim Sergeyevich Sergeyev, Novgorod, Russia, for a "millimeter-wave communication system with directional antenna and one or more millimeter-wave reflectors." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of millimeter-wave communication systems and methods for communicating using millimeter-waves are described. In some embodiments, a directional antenna (102) may direct millimeter-wave signals substantially in a horizontal plane (115), and one or more reflectors (104) may be positioned to reflect the millimeter-wave signals to user devices (108)." The patent application was filed on May 23, 2006 (12/301,556). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,178&OS=8,149,178&RS=8,149,178 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Hewlett-Packard Development Assigned Patent for Display ALEXANDRIA, Va., April 6 -- Hewlett-Packard Development, Houston, has been assigned a patent (8,149,183) developed by Peter James Fricke, Corvallis, Ore., and Alan R. Arthur, Salem, Ore., for a display.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Various embodiments and methods relating to driving a stacked arrangement of display panels are disclosed." The patent application was filed on July 31, 2007 (11/831,014). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,183&OS=8,149,183&RS=8,149,183 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Intel Assigned Patent ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,148,239) developed by Alejandro Varela, Phoenix, Troy L. Harling, Gresham, Ore., and Daniel E. Vanlare, Phoenix, for an "offset field grid for efficient wafer layout." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines." The patent application was filed on Dec. 23, 2009 (12/646,459). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,148,239.PN.&OS=PN/8,148,239&RS=PN/8,148,239 Written by Shabnam Sheikh; edited by Jaya Anand.

*** Electro Scientific Industries Assigned Patent ALEXANDRIA, Va., April 6 -- Electro Scientific Industries, Portland, Ore., has been assigned a patent (8,148,211) developed by five co-inventors for a "semiconductor structure processing using multiple laser beam spots spaced on-axis delivered simultaneously." The co-inventors are Kelly J. Bruland, Portland, Ore., Brian W. Baird, Oregon City, Ore., Ho Wai Lo, Portland, Ore., Stephen N. Swaringen, Rockwall, Texas, and Frank G. Evans, Dundee, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects the semiconductor substrate and a second laser beam that propagates along a second laser beam axis that intersects the semiconductor substrate. The method simultaneously directs the first and second laser beams onto distinct first and second structures in the row. The method moves the first and second laser beam axes relative to the semiconductor substrate substantially in unison in a direction substantially parallel to the lengthwise direction of the row, so as to selectively irradiate structures in the row with one or more of the first and second laser beams simultaneously." The patent application was filed on Feb. 4, 2005 (11/051,500). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,148,211.PN.&OS=PN/8,148,211&RS=PN/8,148,211 Written by Shabnam Sheikh; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,148,959) developed by Jeffrey A. Carlson, Portland, Ore., and Edward P. Osburn, Tigard, Ore., for a "microprocessor die with integrated voltage regulation control circuit." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor." The patent application was filed on Feb. 8, 2011 (13/022,959). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,148,959&OS=8,148,959&RS=8,148,959 Written by Kusum Sangma; edited by Anand Kumar.

*** Semiconductor Components Industries Assigned Patent ALEXANDRIA, Va., April 6 -- Semiconductor Components Industries, Phoenix, has been assigned a patent (8,148,966) developed by Gang Chen, Hong Kong, and Tod F. Schiff, Portland, Ore., for a "power supply control circuits including enhanced ramp pulse modulation." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A power supply control circuit includes a latch including a first latch input for receiving a first logic signal, a second latch input for receiving a second logic signal, and a latch output for providing an output signal. The power supply control circuit further includes a controller coupled to the first and second latch inputs. The controller is configured to generate the first logic signal based on an error signal and a threshold signal and in response to an off-time signal to control timing between pulses in the output signal. The controller is further configured to select one of the error signal and the threshold signal and to generate the second logic signal based on a ramp signal and the one of the error signal and the threshold signal to control a width of the pulse." The patent application was filed on Aug. 24, 2010 (12/862,414). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,148,966&OS=8,148,966&RS=8,148,966 Written by Kusum Sangma; edited by Anand Kumar.

*** Xerox Assigned Patent ALEXANDRIA, Va., April 6 -- Xerox, Norwalk, Conn., has been assigned a patent (8,149,017) developed by David L. Knierim, Wilsonville, Ore., for a "low-voltage to high-voltage level translation using capacitive coupling." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A voltage level translator circuit has a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor. A high-voltage driving circuit has two low-voltage input signals, two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal, two level translators, a first level translator corresponding to the high-side drive signal, and a second level translator corresponding to the low-side drive signal, the level translators including a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor." The patent application was filed on June 25, 2010 (12/823,666). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,017&OS=8,149,017&RS=8,149,017 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,148,786) developed by eight co-inventors for a "complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate." The co-inventors are Jack Kavalieros, Portland, Ore., Annalisa Cappellani, Portland, Ore., Justin K. Brask, Portland, Ore., Mark L. Doczy, Beaverton, Ore., Matthew V. Metz, Hillsboro, Ore., Suman Datta, Beaverton, Ore., Chris E. Barns, Portland, Ore., and Robert S. Chau, Beaverton, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.." The patent application was filed on June 29, 2009 (12/493,291). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,148,786&OS=8,148,786&RS=8,148,786 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Recessed Channel Array Transistor (RCAT) Structures ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,148,772) developed by four co-inventors for a "recessed channel array transistor (RCAT) structures." The co-inventors are Brian S. Doyle, Portland, Ore., Ravi Pillarisetty, Portland, Ore., Gilbert Dewey, Hillsboro, Ore., and Robert S. Chau, Beaverton, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure." The patent application was filed on Jan. 31, 2011 (13/017,309). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,148,772&OS=8,148,772&RS=8,148,772 Written by Kusum Sangma; edited by Anand Kumar.

*** Applied Materials Assigned Patent ALEXANDRIA, Va., April 6 -- Applied Materials, Santa Clara, Calif., has been assigned a patent (8,148,663) developed by six co-inventors for an "apparatus and method of improving beam shaping and beam homogenization." The co-inventors are Bruce E. Adams, Portland, Ore., Samuel C. Howells, Portland, Ore., Dean Jennings, Beverly, Mass., Jiping Li, Palo Alto, Calif., Timothy N. Thomas, Portland, Ore., and Stephen Moffatt, St. Lawrence, United Kingdom.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention generally relates to an optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. Typically, the anneal regions may be square or rectangular in shape. Generally, the optical system and methods of the present invention are used to preferentially anneal one or more regions found within the anneal regions by delivering enough energy to cause the one or more regions to re-melt and solidify." The patent application was filed on July 31, 2007 (11/888,433). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8148663.PN.&OS=PN/8148663&RS=PN/8148663 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Power Saving Operation of Always-connected Wireless Roaming ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,149,747) developed by Kapil Sood, Beaverton, Ore., and Tsai James, Beaverton, Ore., for a "power saving operation of always-connected wireless roaming." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatuses enable maintaining wireless connectivity while the wireless client device is in a power save mode. The system includes a host operating system (OS) that handles wireless connections while the device is executing in normal operation, and an embedded agent that handles the wireless connections when the device switches to power saving operation and the host OS switches to a sleep or standby state. The system detects a change in the power save mode and triggers an exchange of session context information between the host OS and the embedded agent (from the host OS to the embedded agent when the system enters the power save mode, and from the embedded agent to the host OS when the system returns to normal operation from the power save mode). The system also triggers the switching of management consistent with the passing of session context information." The patent application was filed on Sept. 28, 2007 (11/864,688). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,747&OS=8,149,747&RS=8,149,747 Written by Arpi Sharma; edited by Anand Kumar.

*** Intel Assigned Patent for Battery Level Based Configuration of a Mobile Station by a Base Station ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,149,746) developed by four co-inventors for a "battery level based configuration of a mobile station by a base station." The co-inventors are Mustafa Demirhan, Hillsboro, Ore., Ali Taha Koc, Hillsboro, Ore., Shweta Shrivastava, Beaverton, Ore., and Rath Vannithamby, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the present invention provide methods and systems for battery level based configuration of a mobile station by a base station. Other embodiments may be described and claimed." The patent application was filed on Aug. 28, 2006 (11/467,881). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,746&OS=8,149,746&RS=8,149,746 Written by Arpi Sharma; edited by Anand Kumar.

*** Siga Technologies Assigned Patent ALEXANDRIA, Va., April 6 -- Siga Technologies, Corvallis, Ore., has been assigned a patent (8,148,428) developed by four co-inventors for an "antiviral drugs for treatment of arenavirus infection." The co-inventors are Dennis E. Hruby, Albany, Ore., Tove C. Bolken, Keizer, Ore., Sean Amberg, Corvallis, Ore., and Dongcheng Dai, Corvallis, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Compounds, methods and pharmaceutical compositions for treating viral infections, by administering certain novel compounds in therapeutically effective amounts are disclosed. Methods for preparing the compounds and methods of using the compounds and pharmaceutical compositions thereof are also disclosed. In particular, the treatment and prophylaxis of viral infections such as caused by hemorrhagic fever viruses is disclosed, i.e., including but not limited to, Arenaviridae (Junin, Machupo, Guanarito, Sabia, Lassa, Tacaribe, and Pichinde), Filoviridae (Ebola and Marburg viruses), Flaviviridae (yellow fever, Omsk hemorrhagic fever and Kyasanur Forest disease viruses), and Bunyaviridae (Rift Valley fever)." The patent application was filed on March 2, 2007 (12/281,081). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,148,428&OS=8,148,428&RS=8,148,428 Written by Arpi Sharma; edited by Anand Kumar.

*** Intel Assigned Patent for Device Power Management in a Wireless Network ALEXANDRIA, Va., April 6 -- Intel, Santa Clara, Calif., has been assigned a patent (8,149,750) developed by Michelle X. Gong, Sunnyvale, Calif., and Minyoung Park, Portland, Ore., for a "device power management in a wireless network." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In various embodiments of the invention, a device in a wireless communications network may negotiate with a network controller to determine when the device may enter a power save mode. The power save mode may include period(s) in which the device is in a low power state in which it cannot transmit or receive, and period(s) in which it is in an operational state in which it can transmit and/or receive." The patent application was filed on April 7, 2009 (12/384,638). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,149,750&OS=8,149,750&RS=8,149,750 Written by Arpi Sharma; edited by Anand Kumar.

*** Rigel Pharmaceuticals Assigned Patent ALEXANDRIA, Va., April 6 -- Rigel Pharmaceuticals, South San Francisco, Calif., has been assigned a patent (8,148,525) developed by eleven co-inventors for a "2,4-pyrimidinediamine compounds and their uses." The co-inventors are Rajinder Singh, Belmont, Calif., Ankush Argade, Foster City, Calif., Donald G. Payan, Hillsborough, Calif., Susan Molineaux, San Mateo, Calif., Sasha J. Holland, San Francisco, Jeffrey Clough, Redwood City, Calif., Holger Keim, Irvine, Calif., Somasekhar Bhamidipati, Foster City, Calif., Catherine Sylvain, Burlingame, Calif., Hui Li, Santa Clara, Calif., and Alexander B. Rossi, Reedsport, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention provides 2,4-pyrimidinediamine compounds that inhibit the IgE and/or IgG receptor signaling cascades that lead to the release of chemical mediators, intermediates and methods of synthesizing the compounds and methods of using the compounds in a variety of contexts, including in the treatment and prevention of diseases characterized by, caused by or associated with the release of chemical mediators via degranulation and other processes effected by activation of the IgE and/or IgG receptor signaling cascades." The patent application was filed on April 16, 2010 (12/762,178). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,148,525&OS=8,148,525&RS=8,148,525 Written by Arpi Sharma; edited by Anand Kumar.

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